| Job Details |
| Post Available |
PM (ASIC Design)
(very urgent) |
|
|
| Company or Consultant |
A Client of BMC India |
|
|
| Company Profile |
A Fortune 500 Company. (
For more detail about the opening, pls contact us-91-0-9811964222
) |
|
|
| Vacancy
Explanation |
Architecture,
design & RTL implementation for multimillion gate
SoC based ASIC / FPGAs (Language : Verilog / VHDL /
System Verilog).System Level, functional and formal
verification (Language : Verilog & PLI, HVL, PSL,
VERA, System C, C++ |
| Preferred Candidate |
Syntheses &
Timing closure in 0.13u or 90nm ASIC technology libraries
or FPGA implementations in Xilinx or Altera (Cadence
/ Synopsys / IBM / Mentor flow)
DFT methodology (Mentor / Synopsys)
Physical design, timing closure |
|
|
| Minimum Experience |
4 years |
|
|
| Maximum Experience |
10 years |
|
|
| Reimbursement |
Negotiable |
|
|
| Vacancy for |
Delhi/NCR |
|
|
| Qualification |
Any-Engineering,Any Engineering
|
| Function |
Team Lead/Tech Lead |
| Keywords |
Verilog & PLI, HVL,
PSL, VERA, System C, C++ |
|
|
| Reference |
ASIC-WEB |
|
|
| Contact Details |
| Name |
Ashok Sharma |
| Email Contact |
resumes@internet-jobs-search.com
|
| Address |
BMC, New Delhi, India
|
| Posted on |
11 Nov' 2005 |
|
|
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|
